1. Technical Field
The invention relates generally to integrated circuits, and more specifically, to integrated circuits having built-in test circuits.
2. Background Art
As technology advances, more circuits and corresponding functions are being integrated onto one chip, or integrated circuit. Consequently, the need for adequate testing of the various functions on each integrated circuit has become increasingly important.
In general, integrated circuit testing requires a chip to undergo electrical and thermal stress for several hours in order to improve the long term reliability of the chips in the system. That is, when a chip is exposed to electrical and thermal conditions beyond the nominal operating range, the life of the chip is accelerated and failures may be detected prior to the next level of system assembly.
Electrical stress conditions may consist of powering and/or cycling the chip through several power supply values while at the same time providing test patterns to the logic and memory arrays on the integrated circuit to maximize the internal node switching whenever possible. One method for testing the effectiveness of the logic and arrays are through embedding self-test circuits, which are also built onto the integrated circuit. Such schemes are frequently referred to as Built-In Self Test (BIST), which test both memory arrays (ABIST) and logic LBIST). U.S. Pat. No. 5,173,906, issued December 1992 to Dreibelbis et al. depicts an example of a built-in self test circuit for integrated circuits that provides a programmable fail/no-fail result of the corresponding memory circuits.
Similarly, thermal stress conditions are generally tested by extending the chip over a wide temperature range, cycling the circuits through several temperature operating points, and following a predefined highly effective temperature profile. In the past, burn-in ovens were used to monitor and control the temperature environment surrounding the several chips undergoing stress. Burn-in ovens, though, are an expensive burn-in process because of the equipment cost and because of the time the equipment is required to be dedicated to a relatively small number of chips. One solution to this problem is found in U.S. Pat. No. 5,309,090 issued May 1994 to Lipp. The Lipp reference discloses heating elements that may be integrated onto the integrated circuit. The temperature is controlled by a controller that is also integrated onto the circuit. A disadvantage of using the heating element as disclosed by Lipp, though, is that either extra circuitry must be incorporated onto the chip to heat the chip, thus utilizing additional space; or existing circuitry (such as output buffers) that are not in use must be turned on to supply the power needed to heat the integrated circuit, thus utilizing excess current and power.